Vivado Design Suite Fixed Review

Vivado supports multiple methodologies for defining hardware logic:

During synthesis, Vivado translates the RTL code into a gate-level netlist. It maps generic logical constructs to the specific primitives available on the target Xilinx device (e.g., LUTs, Flip-Flops, DSP slices). vivado design suite

Check out the official Vivado Design Methodology Guide to get started the right way. vivado design suite

Here’s a to Vivado Design Suite (by AMD/Xilinx), from installation to basic FPGA design flow. vivado design suite