c.io.en.poke(false.B) c.clock.step(2) c.io.out.expect(3.U) // unchanged
: A standard library for unit testing Chisel modules, providing a high-level API to poke, peek, and step through hardware simulations. chiselsim
The typical Chisel workflow involves generating Verilog, which is then passed to a third-party simulator. This introduces friction: the abstraction hierarchy is lost in translation to Verilog, and the engineer must rely on the simulator's specific API for testing. ChiselSim aims to close this loop by generating a simulator directly from the Chisel AST (Abstract Syntax Tree), allowing the testbench to remain in Scala and share data structures with the design. ChiselSim aims to close this loop by generating
: Seamless implementation of AXI4/AXI4-Lite interfacing and multi-clock domain designs. Simulation and Verification Frameworks Agile Hardware Development
Hardware Simulation, Chisel, FIRRTL, Agile Hardware Development, Code Generation, Verification.
