A high-speed signal (e.g., a 100 MHz clock) travels on a top-layer trace. Its return current flows directly underneath it on the reference plane (GND). If the trace crosses a split in the ground plane or a moat of vias, the return current is forced to detour. This loop area becomes a loop antenna.
Engineers often reach for shielding cans ("the tin can solution") when emissions tests fail. However, shielding is an admission of defeat in the design phase. It adds cost, weight, and assembly complexity. True EMC mastery focuses on suppression at the source. emc for printed circuit boards
The "Golden Rule" of PCB design is that every signal has a return path. At high frequencies, the return current doesn't follow the path of least resistance—it follows the path of . A high-speed signal (e
| Domain | Golden Rule | | :--- | :--- | | | Never route sensitive signals (reset, clock) near noisy ones (motor drivers, switch-mode supplies). | | Grounding | Use a solid, unbroken ground plane. Do not split analog and digital grounds unless you have a hybrid layer stack. | | Clocking | Keep clock traces short, direct, and surrounded by ground vias. Route them away from I/O. | | Filtering | Place ferrite beads and capacitors directly at the noise source or the connector entry point. | | Return Vias | When a signal changes layers, place a GND via adjacent to the signal via to allow the return current to follow. | | Isolation | For mixed-signal boards (ADC/DAC), partition the board physically, not the ground plane. | This loop area becomes a loop antenna